The PCI‑SIG consortium has kicked off development of PCIe 8.0, the next major revision of the PCI Express standard. While products based on PCIe 7.0 have not yet reached the market, the group is already publishing the first draft of PCIe 8.0, with a final spec expected in 2028.
Like previous generations, PCIe 8.0 doubles the performance of its predecessor. It targets a raw data rate of 256 GT/s and up to 1 TB/s of bi‑directional bandwidth in a 16‑lane configuration—twice as much as PCIe 7.0.
Designed for AI, HPC, and Edge
PCIe is the backbone interface for storage, networking, and graphics, including GPU‑based accelerators. PCI‑SIG says the new spec is being built primarily for AI/ML, high‑speed networking, edge computing, and other bandwidth‑hungry workloads in hyperscale data centers.
“With the increasing data throughput required in AI and other applications, there remains a strong demand for high performance,” said Al Yanes, PCI‑SIG president and chair. “PCIe technology will continue to deliver a cost‑effective, high‑bandwidth, and low‑latency I/O interconnect to meet industry needs”.
In theory, PCIe Gen8 NVMe SSDs could reach sequential speeds of up to 120,000 MB/s, compared with around 28,000 MB/s for a PCIe 6.0 SSD. That’s more than a four‑fold increase over the current generation of high‑end NVMe drives.
Signaling and Physical Layer
PCIe 8.0 continues to rely on PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, first introduced in PCIe 6.0 as a replacement for NRZ. Further refinements to PAM4 are being used to reach the higher transfer rates while managing signal integrity and power.
Development has also focused on:
Connector technology
Latency reduction
Forward error correction (FEC)
Reliability
Protocol‑level bandwidth optimizations
Lower power consumption
Backward compatibility with earlier PCIe generations remains a high priority, so older devices and lanes will still work alongside PCIe 8.0 hardware.
Client vs. Server: Different Adoption Curves
On desktops and notebooks, PCIe adoption has largely settled at PCIe 5, with little urgency to move to PCIe 6. Most consumer workloads—gaming, general productivity, and even many creative apps—do not yet need the extra bandwidth that PCIe 6 offers.
On the server side, the picture is different. High‑throughput storage, networking, and AI accelerators benefit directly from the higher bandwidth and PAM4 efficiency. Upcoming server CPUs, including AMD Zen 6‑based EPYC and Intel Diamond Rapids Xeon processors arriving this year, are expected to support PCIe 6.0. PCIe 7.0 is already finished and ready for OEMs when they are prepared to adopt it, while PCIe 8.0 is now in early development.
Why a New Spec So Soon?
PCI‑SIG announced PCIe 7.0 nearly four years ago, and no PCIe 7.0 products are on the market yet. The move to start work on PCIe 8.0 early reflects the long lead times for chip design, validation, and ecosystem adoption, especially in data centers where AI and high‑performance computing are driving demand for faster I/O.
PCIe 8.0 is aimed squarely at the future layer of AI and HPC infrastructure, where bandwidth is already becoming a bottleneck and earlier generations will not be enough in a few years.
